Beyond HBM: SiC, EUV masks and 3D transistors

SiC and silicon wafers

For substrate makers, surface quality is the product. Polish roughness, scratches, sub-surface damage and epitaxial step morphology all determine device yield downstream. These are AFM-native measurements, limited today by how much area a single tip can cover.

EUV masks and high-NA resist

EUV mask blanks must be smooth at the sub-nanometre level. High-NA EUV resists are thin, and an electron beam can shrink the very resist it is measuring. AFM measures profile height mechanically, without that interaction.

GAA and CFET

As transistors move from FinFET to gate-all-around and stacked CFET, more process steps depend on nanometre-scale surface topography, such as recess and planarity after CMP. Direct AFM data on those surfaces becomes part of process development and control.

The common thread

Each of these needs direct, nanometre-scale surface data over more area than a single tip can cover. Parallel, miniaturized AFM is a platform for all of them; HBM and hybrid bonding are where we start.