Technical note4 min read
Below 2 µm pitch: where optical metrology needs an AFM reference
Hybrid-bonding pitch keeps shrinking, and research is already below 1 µm. What happens to pad-level metrology as pads approach the optical resolution limit.
Akshay Harlalka,
Interconnect density is advanced packaging’s version of Moore’s law. Each generation packs bond pads closer: from microbumps at tens of microns, to hybrid bonding at 4.5–9 µm in today’s leading platforms, toward roughly 3–5 µm on announced roadmaps, and 250–400 nm in wafer-to-wafer research.
| Pitch | Where it appears | Pad-level metrology |
|---|---|---|
| ~10 µm and above | Microbumps, early hybrid bonding | Optical tools work well |
| 4.5–9 µm | Intel Foveros Direct, TSMC SoIC-X | Optical works, calibrated against AFM |
| ~3–5 µm | Announced roadmaps | Optical works; copper/dielectric phase offsets need AFM calibration |
| ≤ 2 µm | Fine-pitch roadmaps | Pads span a few optical resolution elements; AFM becomes the pad-level reference |
| < 1 µm | R&D | Pads near the optical resolution limit; AFM is the pad-level reference |
Why the limit matters
Visible light cannot resolve features much smaller than about half its wavelength. As pads shrink toward a micron, each pad occupies only a few resolution elements. Optical tools still produce numbers, through models of how light reflects off copper and oxide, but those models need a trusted reference, and that reference is AFM.
This is not an argument against optical metrology. Fast optical tools will keep doing the heavy lifting. The point is that the reference has to keep up: if AFM can only sample a few sites per lot, the calibration and the process control built on it are only as dense as those sites.
What fabs need
- Direct 3D height at pad level, independent of optical models.
- Enough sites per wafer to see within-wafer and edge effects.
- Data fast enough to act on before the next wafer is polished.
That combination is what parallel AFM at the tool is designed to deliver.
Sources
- Pitch ranges compiled from public roadmaps (Intel Foveros Direct, TSMC SoIC) and published research. Illustrative.
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